PhysAddr Global:1;
PhysAddr FaultOnWrite:1;
PhysAddr PermWrite:1; // High-level permission-based write access
- PhysAddr Avail:1;
+ PhysAddr AddressOnly:1;
PhysAddr Addr:20;
};
maskout = 0;
flagsout = 0;
- if (maskin.Valid) {
- maskout.Valid = 1;
- flagsout.Valid = flagsin.Valid;
- }
-
- if (maskin.FaultOnWrite) {
- maskout.FaultOnWrite = 1;
- flagsout.FaultOnWrite = flagsin.FaultOnWrite;
- }
+ maskout.Valid = maskin.Valid;
+ maskout.FaultOnWrite = maskin.FaultOnWrite;
+ maskout.AddressOnly = maskin.AddressOnly;
+ maskout.CacheDisable = maskin.Uncached;
+
+ flagsout.Valid = flagsin.Valid;
+ flagsout.FaultOnWrite = flagsin.FaultOnWrite;
+ flagsout.AddressOnly = flagsin.AddressOnly;
+ flagsout.CacheDisable = flagsin.Uncached;
if (maskin.Writeable) {
maskout.Writeable = 1;
Mem::PTEFlags ret = 0;
ret.Valid = Valid;
- ret.User = User;
if (Valid) {
+ ret.User = User;
ret.Readable = 1;
ret.Writeable = PermWrite;
ret.Executable = 1;
+ ret.Uncached = CacheDisable;
ret.FaultOnWrite = FaultOnWrite;
+ ret.AddressOnly = AddressOnly;
}
return ret;
return Dirty;
}
+ bool addronly_pte()
+ {
+ return AddressOnly;
+ }
+
enum {
page_size = Arch::page_size,
page_shift = Arch::page_shift,